1. Field of the Invention
The present invention relates to an inverter circuit, and more specifically, an inverter circuit with a switching device, in which a gate is driven by a high-voltage integrated circuit.
2. Description of the Related Art
With the broader use of low-power Insulated Gate Bipolar Transistor (IGBT) inverters of about 3.7 Kw or lower even in household appliances, more attention is being given to providing high efficiency and low electro-magnetic interference (EMI) noise and minimizing the cost, the size, and the weight of the inverters. Also, a high-voltage integrated circuit (HVIC) for a high-voltage gate driver is increasingly being used with the IGBT inverters. The HVIC enables not only reliable control of pulse width modulation (PWM) but also simplifies circuit construction and reduces costs.
However, a gate driver implemented as an HVIC may generate latched gate output signals, which potentially could destroy the entire system. This is because a reference voltage, which is applied to the HVIC used for driving a gate, is floated and fluctuates at every moment an IGBT is switched. Such a latch phenomenon may occur due to an inverter power circuit and its parameters, a gate driving circuit and its parameters, the switching characteristics of the IGBT, the operating conditions of an inverter, and the like.
FIG. 1 is a schematic diagram of a conventional, previously developed inverter circuit. FIG. 2 is a timing diagram showing an input signal and output signals of an HVIC at the inverter circuit of FIG. 1, wherein the output signals are generated when latch-on and latch-up occur, respectively.
Referring to FIG. 1, an output terminal O of an HVIC 110 is connected to a gate terminal of an IGBT 130, which is a switching device, through a gate series resistor Rg. A gate control signal Vg is output through the output terminal O of the HVIC 110. A capacitor 170, which generates an input DC-link voltage VDC, is connected to a collector terminal of the IGBT 130 through a switch S1 172. Also, an inductive load Lload 164 is connected to a node D, which is connected to an emitter terminal of the IGBT 130. A stray inductor 161 having an inductance Lstray, a diode 162, and a shunt resistor 163 having a resistance Rshunt are connected in series to the node D. The node D is also connected to a node S, which is both an output terminal of the HVIC 110 and a terminal of a bootstrap circuit.
The HVIC 110 includes two input terminals IN and C. The HVIC 110 receives a control input signal Vin from a controller 120 through the input terminal IN and receives an integrated circuit driving voltage VCC through the input terminal C. A level-shift MOS transistor 155, which is located inside the HVIC 110, transmits to an edge triggering block 111 the control input signal Vin, which is input from the input terminal IN, through a switching operation. The edge triggering block 111 senses a falling edge of the received control input signal Vin and maintains the control input signal IN until the next signal is input. The signal maintained by the edge triggering block 111 is input to the gate terminal of the IGBT 130 through a buffer 112 and the gate output terminal O.
The HVIC 110 is connected to the bootstrap circuit, which includes a capacitor 151, a bootstrap resistor 152, a bootstrap diode 153, and a bootstrap capacitor 154, which are connected in series. The capacitor 151 transmits energy to a secondary power source of the HVIC 110, i.e., the bootstrap capacitor 154. The bootstrap resistor 152 prevents rapid charging of the bootstrap capacitor 154. The bootstrap diode 153 protects the HVIC 110 and low-voltage devices from high voltage when the IGBT 130 is switched off. The bootstrap capacitor 154 functions as the secondary power source of the HVIC 110 and is connected to terminals B and S of the HVIC 110.
In the foregoing conventional inverter circuit, if a latch phenomenon occurs in the IGBT 130, the gate control signal Vg output from the output terminal O of the HVIC 110 is not affected by the control input signal Vin output from the controller 120. Thus, the IGBT 130 does not perform appropriate switching operations. That is, even if the HVIC 110 receives the control input signal Vin from the controller 120 as shown in (a) of FIG. 2, at time t6 where latch-on occurs, the gate control signal Vg output from the output terminal O of the HVIC 110 is not held in an off-signal state and abnormally generates an on-signal, as shown in (b) of FIG. 2. Also, at time t4 where latch-up occurs, the gate control signal Vg output from the output terminal O of the HVIC 110 is held in an off-signal state without generating an on-signal, as shown in (c) of FIG. 2. Therefore, the IGBT 130 is abnormally switched on at time t6 even though it should be switched off when the latch-on occurs, and is abnormally switched off at time t4 even though it should be switched on when the latch-up occurs.
FIGS. 3A and 3B are signal diagrams showing an input signal waveform of an HVIC and a collector current of an IGBT when latch-up and latch-on occur, respectively.
Referring to FIG. 3A, even if a control input signal Vin corresponding to switching-on data is input to an HVIC 110 at time t4, the collector current IC of an IGBT 130 does not increase. As is known, such latch-up occurs because a very high steady-state reverse voltage is generated at terminal S of the HVIC 110 due to a voltage drop caused by freewheeling current IFW flowing through diode 162 and a shunt resistor 163 between times t3 and t4.
Referring to FIG. 3B, even if a control input signal Vin corresponding to switching-off data is input to the HVIC 110 at time t6, the collector current IC of the IGBT 130 decreases instantly and thereafter starts increasing again. As is known, such latch-on occurs due to forward conduction of parasitic diodes inside the HVIC 110 in an over-stress condition, such as no-load or rapid charging of the bootstrap capacitor 154. In the over-stress condition, current flows through an internal Electro Static Discharge (ESD) diode located between two terminals B and S of the HVIC 110, and the high-side IGBT 130 is turned on due to the current.
Therefore, latch-on or latch-up may prevent steady switching operations of an inverter circuit, in which an IGBT 130 is switched by an HVIC 110, thus potentially destroying elements of the inverter device.